The present invention relates to fabrication of a capacitor in the layers of metalization on a semiconductor chip and, more specifically, to a metal capacitor made as part of a copper dual damascene fabrication process which includes forming a structure for interconnecting the capacitor into adjacent circuitry on the semiconductor wafer and to a metal capacitor that has a folded configuration.
As front end of the line (FEOL) components of a chip have become progressively smaller, more numerous, more complex and faster, the number of back end of the line (BEOL) layers has increased. Because of the size and density of the FEOL devices, the width, and hence, the cross sectional areas, of the interconnect lines in the BEOL layers has been reduced. However, reducing such cross sectional area raises the resistance of the aluminum lines heretofore used. Thus, recently there has been a movement to using copper in the BEOL process because of its low resistance qualities. Use of copper has required the adoption of a whole new fabrication technology based on copper dual damascene manufacturing techniques. With these developments has come the related desire to include passive circuit elements, e.g., decoupling capacitors, formerly placed in the packaging of a semiconductor chip right on the chip to take advantage of the new opportunities for increased speed that copper offers.
Fabrication of capacitors in the context of new dual damascene metal fabrication processes creates certain challenges. Providing capacitors having a desired capacitance in the space or xe2x80x9cfootprintxe2x80x9d available can be problematic. Also, to avoid unacceptable variation in capacitance due to variation in via depth, width, and slope of the materials used to make the capacitor in a known dual damascene fabrication process, adequate control of reactive ion etch (RIE) selectivity is a challenge and related process control issues are created.
It is another objective of the present invention to provide a method of fabricating a metal capacitor on a chip as part of a copper dual or single damascene manufacturing process.
It is yet another objective to provide a method of fabricating a precision metal capacitor on a semiconductor chip as part of a copper dual or single damascene manufacturing process.
It is still another objective of the present invention to provide a capacitor with a unique strap contact for the bottom plate of the capacitor.
It is still a further objective of the present invention to provide a capacitor structure that maximizes use of available space on a semiconductor wafer to thereby increase its capacitance.
The present invention accomplishes these and other objectives by providing a contact for the bottom plate of a capacitor fabricated on a semiconductor wafer with an interconnect line adjacent, but spaced from, the bottom plate and a strap contact that connects the bottom plate to the interconnect line.
Another aspect of the present invention is a capacitor structure in a semiconductor device. The structure comprises an insulating layer having a trench and at least two vias formed in the trench. A bottom plate lines the trench and the at least two vias. A dielectric layer is positioned above the bottom plate and a top plate is positioned above the dielectric layer.
Yet another aspect of the present invention is a method of forming a capacitor on a wafer having devices fabricated up through a metal interconnect level and having an insulator level with at least one via and trench formed therein. The method comprises the steps of: (a) depositing a first barrier layer; (b) depositing a dielectric material on the barrier layer; (c) depositing a second barrier layer on the dielectric material; and (d) depositing a metal conductor on the second barrier layer.
Still another aspect of the present invention is a method of forming a capacitor on a wafer having devices fabricated up through a metal interconnect level having an interconnect and a surface. The method comprises the steps of: (a) depositing an insulator on the metal interconnect level, the insulator having a top surface; (b) forming in the insulator a via that intersects the interconnect and a trench adjacent the via; (c) depositing a barrier layer in the via and in the trench; (d) depositing a dielectric material above the barrier layer; and (e) depositing a metal conductor above the dielectric material.